Monday, February 3, 2020

The Angelov MESFET Model built for QUCS Studio

In the present entry, an Angelov MESFET model built for the QUCS Studio CAD tool will be presented.
This model is based in the VERILOG-A built in capabilities that offers QUCS Studio.
The technical background that is necessary to understand the equations and expressions that model the behavior of MESFET transistors can be found, in part, in the following paper:

An Angelov Large Signal Model and its Parameter Extraction Strategy for GaAs HEMT
Yan Wang Wenyuan Zhang
Tsinghua University

The paper is available in this link:

The file containing the brief explanation about the process of modelling can be found in this link:

The files that are described in the previous document can be accessed in this link:

Thursday, November 21, 2019

Behavioral models of the basic logic gates based on Verilog AMS.

In a new entry in the section "Verilog AMS Files", they are available for downloading the files that provide the possibility of simulate logic gates, the three basic ones, AND gate, OR gate and the inverter, from the behavioral point of view.

Mixed simulation is not implemented in QUCS Studio. Meaning that it is possible to work with logic circuits, but using the chronogram aproximation. One digital circuit in a QUCS Studio schematic can not be analyzed using transient analysis.

The logic gates coded in Verilog AMS and completed with some lumped elements offer the posibility of simulating using transient analysis with the advantange of the behavioral approximation. The same function for the logic gates implemented using the phisycal model (i. e. building the logic gates with the transistors that compose them physically) will take, on average, more time of analysis.

Wednesday, November 20, 2019

A Voltage Controlled Voltage Source with a Table defined dependency designed in Verilog AMS

As a second part of the post from a few days back, this time it is presented a voltage controlled voltage source with a table defined dependency. In many cases, there are SPICE models that include this type of controlled source as a part of the circuit, and this element, designed basically in Verilog AMS module, allows to cover this type of necesities.

Go and visit the "Verilog AMS Files" section of this site and you will find the links to the documentation and the files that are necessary to run in QUCS Studio this new controlled source.

Saturday, November 16, 2019

A New Voltage Controlled Voltage Source with polynomial dependency for QUCS Studio

In QUCS Studio it is possible to find the basic controlled sources that are common in all the CAD tools. But there are other options for controlled sources that would be interesting for modelling devices and that it can be modeled in QUCS Studio using the Verilog AMS capabilities of the tool.

In the section "Verilog AMS Files" of this site it is now possible to find the description of the design process and the files necessaries to work with a new type of Voltage Controlled Voltage Source for QUCS Studio where the dependency is a polynomial expression of a determined independent voltage.

Wednesday, November 13, 2019

An improvement in the DCDC Model for QUCS Studio

In the previous DCDC spice model published in this site there were included two different aproximations that were rather inaccurate and could provoke convergence problems in transient analysis. After testing the first design, many of the failures in the transient analysis were resolved changing the independent voltage sources included in the model.

In this new model these inacurracies that are the existence of these independent voltage source have been resolved and the convergence problems explained before have been reduced significantly.

Until the number of tests are enough to declare the model free of convergence issues, this new approximation to the solution is definetly an improvement because It is better in terms of stability and it is more robust regarding the convergence problems.
To test the model, the previous test file can be used directly, replacing in the project folder the old model file for the new one.

Visit the "SPICE and Models" page and you will find the link for downloading the new DCDC model.

Note: It is still pending to include the characterization of several dynamic performances like the rise and the fall time, and some other parameters like the voltage levels in the output & input pinnes in all the situations. It is foreseen to include these parameters in the next issue of the model.

Saturday, September 21, 2019

Improving convergence problems in the harmonic balance analysis

Convergence problems in harmonic balance analysis are a classic. I think every single human being involved in this stuff have struggled with them in many occasions. You will find plenty of technical papers talking about it. But most of them describe the issue in terms of the mathematical algorithm that is used to build the harmonic balance analysis in the CAD simulators. Not many of them help indeed to understand what can be done once the simulation has failed to converge.
Now, in a new entry in the section "Answering some Questions" it is available for downloading a brief studio regarding this problem, but focused in the case of QUCS Studio, using several examples of circuits and describing the problems that you will find when the convergence of the harmonic balance is an issue.

It is related to a question sent by email to the email address of this site.

Monday, July 1, 2019

Some Verilog AMS examples

Since this entry, some verilog AMS files examples are available in the site. (See the "Verilog AMS Files" menu) They are the following:
The first one, is a basic DCDC model. Similar to the one presented in the "SPICE and Models" menu of the site.
The second one is a voltage reference. This model allows to regulate positive values and also negatives ones. The test file is also included in the link for downloading.
The third one is a basic variagle gain amplifier. The test file is included also.