Some Verilog AMS examples

Since this entry, some verilog AMS files examples are available in the site. (See the "Verilog AMS Files" menu) They are the following:
The first one, is a basic DCDC model. Similar to the one presented in the "SPICE and Models" menu of the site.
The second one is a voltage reference. This model allows to regulate positive values and also negatives ones. The test file is also included in the link for downloading.
The third one is a basic variagle gain amplifier. The test file is included also.